Matthieu Mutz

Technology Officer

2022

I'm a Technology Officer at DeeptechXL. DeeptechXL is an early-stage venture capital impact fund. We invest in companies that develop complex hardware to have a large societal impact. We help our portfolio companies succeed by providing capital, expertise, and network. Please reach out if you are a founder active in our focus area: Sectors: Energy, health, agri and security Technologies: Photonics, quantum, manufacturing, nano, advanced materials Stage: Seed and Series A

Technology Scout and Entrepreneur In Residence

2020 - 2022

System Design Engineer

2018 - 2020

Founder and General Manager

2011 - 2018

Blinksight is a startup developing ultra-precise indoor location technology based on Ultra Wide Band impulse radar. Thanks to its homebrew RF SoC, Blinksight delivers turn key system solutions that enable sub-10cm real time location accuracy. Key areas of responsibility: • General company management: strategic development, funding, legal contracts, accounting • UWB technology and product development (5 issued patents) • System architecture • Location algorithms and software

Senior Design Engineer

2007 - 2010

Participation in the architecture definition and hardware design of the GSM/Edge transmit part of a multi-mode 45 nm RFCMOS transceiver. Key areas of responsibility: • Architecture definition of digital transmit lineup to meet critical performance targets • Digital signal processing specification and modeling using Matlab • RTL description of design using Verilog language • Verification in RTL simulation environment • Logical synthesis including constraints definition • Support to the physical implementation • Technical interface to analog design teams Acquired knowledge: • Cellular radio standards • RF mixed signal design methods • Low power digital design • Work in a multi-cultural team: moved 6 monthes to Austin (TX)

Digital design engineer

2005 - 2007

• Architecture definition for a Secure Stream Processor dedicated to securd stream (de)multiplexing and (de)scrambling in next-generation set-top-boxes and digital televisions • Participation in the hardware design of a multi-standard channel decoder IP for digital television applications. • Architecture definition and hardware design of the link layer components of a DVB-H receiver. Key areas of responsibility: • Architecture definition at IP block level • System level modeling and hardware / software partitionning • RTL design description using VHDL and Verilog languages • Design verification in digital simulation environment • Logical synthesis including constraints definition • Support to the physical implementation team • In-lab verification of hardware functionality on engineering samples Acquired knowledge: • SoC architecture and infrastructure • System level modeling and hardware / software partitionning • Digital design in deep-submicron CMOS • Teamwork

Embedded software engineer

2004 - 2005

Development of low-level software drivers for a MIPS target embedded in a system-on-chip dedicated to PVR set-top-boxes. Key areas of responsibility: • Understanding higher-level API requirements • Getting a deep understanding of underlying hardware blocks to control • Writing drivers in C language • In-lab verification Acquired knowledge: • Hardware / software interface • Embedded real-time software • Software architecture